diff options
| author | Yongbok Kim <yongbok.kim@imgtec.com> | 2015-06-25 00:24:13 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2015-06-26 09:09:42 +0100 |
| commit | 1bf5902de03732d4067c4e90171a1741d6542c45 (patch) | |
| tree | ccf0dcbe22556fcf103ba74bd86f66cd7b5135b0 /target-mips | |
| parent | 2c44b19c199f4ce2f1721120744d3d6e5d01d274 (diff) | |
target-mips: fix {RD, WR}PGPR in microMIPS
rt, rs were swapped
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 8547e2d04d..02c2523207 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -13001,12 +13001,12 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) case RDPGPR: check_cp0_enabled(ctx); check_insn(ctx, ISA_MIPS32R2); - gen_load_srsgpr(rt, rs); + gen_load_srsgpr(rs, rt); break; case WRPGPR: check_cp0_enabled(ctx); check_insn(ctx, ISA_MIPS32R2); - gen_store_srsgpr(rt, rs); + gen_store_srsgpr(rs, rt); break; default: goto pool32axf_invalid; |