diff options
author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-03-24 23:36:18 +0000 |
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committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-03-24 23:36:18 +0000 |
commit | 34ee2edebb992b5d3f7c383a3d0c34f3e75880c8 (patch) | |
tree | a5c28ed0075c7ec5e5440ee81b0fff91c9a724d0 /target-mips | |
parent | 3e736bf4b42fdb19920d348dcd8a1e7c0a0233ca (diff) |
One more bit of mips CPU configuration, and support for early 4KEc
which implemented only MIPS32R1. Thanks to Stefan Weil to insist he's
right on that. :-)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2533 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
-rw-r--r-- | target-mips/translate_init.c | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index b87d8f3b58..6aacfb7e0e 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -65,6 +65,8 @@ struct mips_def_t { int32_t CP0_Config1; int32_t CP0_Config2; int32_t CP0_Config3; + int32_t CP0_Config6; + int32_t CP0_Config7; int32_t CP1_fcr0; }; @@ -83,8 +85,26 @@ static mips_def_t mips_defs[] = .CP1_fcr0 = MIPS_FCR0, }, { - .name = "4KEc", + .name = "4KEcR1", .CP0_PRid = 0x00018400, + .CP0_Config0 = MIPS_CONFIG0, + .CP0_Config1 = MIPS_CONFIG1, + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP1_fcr0 = MIPS_FCR0, + }, + { + .name = "4KEc", + .CP0_PRid = 0x00019000, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR), + .CP0_Config1 = MIPS_CONFIG1, + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .CP1_fcr0 = MIPS_FCR0, + }, + { + .name = "24Kc", + .CP0_PRid = 0x00019300, .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR), .CP0_Config1 = MIPS_CONFIG1, .CP0_Config2 = MIPS_CONFIG2, @@ -153,6 +173,8 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def) env->CP0_Config1 = def->CP0_Config1; env->CP0_Config2 = def->CP0_Config2; env->CP0_Config3 = def->CP0_Config3; + env->CP0_Config6 = def->CP0_Config6; + env->CP0_Config7 = def->CP0_Config7; env->fcr0 = def->CP1_fcr0; return 0; } |