diff options
| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-04-11 18:43:20 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-04-11 18:43:20 +0000 |
| commit | bb928dbef23c7202dcad43aa3efa580ed5c68072 (patch) | |
| tree | ddea59189d2b3567111de6f76c1d18fd7f6e1cb0 /target-mips | |
| parent | d66c7132d23d41796f374aec2f5aff1fb01479ee (diff) | |
target-mips: don't map zero register as a TCG global
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7094 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index f38e576607..7f747d65da 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -8491,7 +8491,7 @@ static void mips_tcg_init(void) return; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - for (i = 0; i < 32; i++) + for (i = 1; i < 32; i++) cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, active_tc.gpr[i]), regnames[i]); |