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author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-19 17:45:43 +0000 |
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committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-19 17:45:43 +0000 |
commit | f469b9db01a1287ae8946159beace6285c2e213a (patch) | |
tree | 1e76bbae17376052ac3216bd915d22c4cbc51f7d /target-mips | |
parent | 5d46d55d4b0f2be4ff7f553013fca4f7980549ab (diff) |
Fix slti/sltiu for MIPS64, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2833 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
-rw-r--r-- | target-mips/op.c | 12 | ||||
-rw-r--r-- | target-mips/translate.c | 4 |
2 files changed, 8 insertions, 8 deletions
diff --git a/target-mips/op.c b/target-mips/op.c index 5e3c797323..c60871afea 100644 --- a/target-mips/op.c +++ b/target-mips/op.c @@ -928,14 +928,14 @@ void glue(op_, name) (void) \ OP_COND(eq, T0 == T1); OP_COND(ne, T0 != T1); -OP_COND(ge, (int32_t)T0 >= (int32_t)T1); +OP_COND(ge, (target_long)T0 >= (target_long)T1); OP_COND(geu, T0 >= T1); -OP_COND(lt, (int32_t)T0 < (int32_t)T1); +OP_COND(lt, (target_long)T0 < (target_long)T1); OP_COND(ltu, T0 < T1); -OP_COND(gez, (int32_t)T0 >= 0); -OP_COND(gtz, (int32_t)T0 > 0); -OP_COND(lez, (int32_t)T0 <= 0); -OP_COND(ltz, (int32_t)T0 < 0); +OP_COND(gez, (target_long)T0 >= 0); +OP_COND(gtz, (target_long)T0 > 0); +OP_COND(lez, (target_long)T0 <= 0); +OP_COND(ltz, (target_long)T0 < 0); /* Branches */ void OPPROTO op_goto_tb0(void) diff --git a/target-mips/translate.c b/target-mips/translate.c index a360d11fc1..0396ac396d 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -921,7 +921,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt, int rs, int16_t imm) { - uint32_t uimm; + target_ulong uimm; const char *opn = "imm arith"; if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { @@ -941,7 +941,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt, #endif case OPC_SLTI: case OPC_SLTIU: - uimm = (int32_t)imm; /* Sign extend to 32 bits */ + uimm = (target_long)imm; /* Sign extend to 32/64 bits */ /* Fall through. */ case OPC_ANDI: case OPC_ORI: |