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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-10 00:51:01 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-10 00:51:01 +0000 |
| commit | beebb570f41693eb3fcda8f31d2532d17c9ef75a (patch) | |
| tree | 07b614cb9262f948052a2ccf13d48e3e35394ced /target-mips | |
| parent | 976a0d0d0d8f8a6f5ba3ac097e8bc4429bd370ae (diff) | |
Fix for the scd instruction, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2799 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index debe17d7c6..449a920a03 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -745,6 +745,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, save_cpu_state(ctx, 1); GEN_LOAD_REG_TN(T1, rt); op_ldst(scd); + GEN_STORE_TN_REG(rt, T0); opn = "scd"; break; case OPC_LDL: |