diff options
| author | Blue Swirl <blauwirbel@gmail.com> | 2012-12-08 17:50:57 +0000 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-12-08 17:50:57 +0000 |
| commit | 536b558f5896ebbd635b57fa393e82faaa32ad52 (patch) | |
| tree | 61756309c1d8f338f943f69bfbe6e6e50128da92 /target-mips | |
| parent | 511c68d3af626cb0a39034cb77e7ac64d3a26c0c (diff) | |
| parent | 19e6c50d2d843220efbdd3b2db21d83c122c364a (diff) | |
Merge branch 'master' of git.qemu-project.org:/pub/git/qemu
* 'master' of git.qemu-project.org:/pub/git/qemu:
target-mips: Fix incorrect shift for SHILO and SHILOV
target-mips: Fix incorrect code and test for INSV
xilinx_uartlite: Accept input after rx FIFO pop
xilinx_uartlite: suppress "cannot receive message"
xilinx_axienet: Implement R_IS behaviour
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/dsp_helper.c | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index e7949c22c0..14daf91950 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \ \ filter = ((int32_t)0x01 << size) - 1; \ filter = filter << pos; \ - temprs = rs & filter; \ + temprs = (rs << pos) & filter; \ temprt = rt & ~filter; \ temp = temprs | temprt; \ \ @@ -3814,17 +3814,18 @@ void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env) rs5_0 = rs & 0x3F; rs5_0 = (int8_t)(rs5_0 << 2) >> 2; - rs5_0 = MIPSDSP_ABS(rs5_0); + + if (unlikely(rs5_0 == 0)) { + return; + } + acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) | ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); - if (rs5_0 == 0) { - temp = acc; + + if (rs5_0 > 0) { + temp = acc >> rs5_0; } else { - if (rs5_0 > 0) { - temp = acc >> rs5_0; - } else { - temp = acc << rs5_0; - } + temp = acc << -rs5_0; } env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32); |