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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-09 18:50:43 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-09 18:50:43 +0000
commita1f6684d6576df57175c18bfe3fbf23cb61922ab (patch)
treef5ecb3e11083c24a3277e92776af7af51767ad79 /target-mips
parent651721b2a55370cf04794d5ce397984c78fc0fec (diff)
target-mips: optimize mflo and mfhi
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6794 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/translate.c25
1 files changed, 12 insertions, 13 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c
index aa6af3209d..5159538359 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1772,42 +1772,41 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
{
const char *opn = "hilo";
- TCGv t0 = tcg_temp_local_new();
if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
/* Treat as NOP. */
MIPS_DEBUG("NOP");
- goto out;
+ return;
}
switch (opc) {
case OPC_MFHI:
- tcg_gen_mov_tl(t0, cpu_HI[0]);
- gen_store_gpr(t0, reg);
+ tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[0]);
opn = "mfhi";
break;
case OPC_MFLO:
- tcg_gen_mov_tl(t0, cpu_LO[0]);
- gen_store_gpr(t0, reg);
+ tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[0]);
opn = "mflo";
break;
case OPC_MTHI:
- gen_load_gpr(t0, reg);
- tcg_gen_mov_tl(cpu_HI[0], t0);
+ if (reg != 0)
+ tcg_gen_mov_tl(cpu_HI[0], cpu_gpr[reg]);
+ else
+ tcg_gen_movi_tl(cpu_HI[0], 0);
opn = "mthi";
break;
case OPC_MTLO:
- gen_load_gpr(t0, reg);
- tcg_gen_mov_tl(cpu_LO[0], t0);
+ if (reg != 0)
+ tcg_gen_mov_tl(cpu_LO[0], cpu_gpr[reg]);
+ else
+ tcg_gen_movi_tl(cpu_LO[0], 0);
opn = "mtlo";
break;
default:
MIPS_INVAL(opn);
generate_exception(ctx, EXCP_RI);
- goto out;
+ return;
}
MIPS_DEBUG("%s %s", opn, regnames[reg]);
- out:
- tcg_temp_free(t0);
}
static void gen_muldiv (DisasContext *ctx, uint32_t opc,