diff options
| author | Michael S. Tsirkin <mst@redhat.com> | 2011-06-14 17:51:11 +0300 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2011-06-15 18:27:15 +0300 |
| commit | befeac45d4d9afb587eca9a27d975db4a7950960 (patch) | |
| tree | aab24c856a3ea944e287d7f2591bb4bab6a56eb4 /target-mips | |
| parent | 35f754620615138aaae0ef72602f84c88fd8de0f (diff) | |
| parent | 0b862cedf36d927818c50584ddd611b0370673df (diff) | |
Merge remote-tracking branch 'origin/master' into pci
Conflicts:
hw/virtio-pci.c
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/exec.h | 4 | ||||
| -rw-r--r-- | target-mips/helper.c | 14 | ||||
| -rw-r--r-- | target-mips/translate_init.c | 4 |
3 files changed, 8 insertions, 14 deletions
diff --git a/target-mips/exec.h b/target-mips/exec.h index b3c5a13f56..607edf12ca 100644 --- a/target-mips/exec.h +++ b/target-mips/exec.h @@ -29,10 +29,6 @@ static inline int cpu_has_work(CPUState *env) has_work = 1; } - if (env->interrupt_request & CPU_INTERRUPT_TIMER) { - has_work = 1; - } - return has_work; } diff --git a/target-mips/helper.c b/target-mips/helper.c index bdc1e53669..0f057c2171 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -272,8 +272,8 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, #if !defined(CONFIG_USER_ONLY) target_phys_addr_t physical; int prot; -#endif int access_type; +#endif int ret = 0; #if 0 @@ -285,21 +285,19 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, rw &= 1; /* data access */ +#if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() correctly */ access_type = ACCESS_INT; -#if defined(CONFIG_USER_ONLY) - ret = TLBRET_NOMATCH; -#else ret = get_physical_address(env, &physical, &prot, address, rw, access_type); qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n", __func__, address, ret, physical, prot); if (ret == TLBRET_MATCH) { - tlb_set_page(env, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, - mmu_idx, TARGET_PAGE_SIZE); - ret = 0; + tlb_set_page(env, address & TARGET_PAGE_MASK, + physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, + mmu_idx, TARGET_PAGE_SIZE); + ret = 0; } else if (ret < 0) #endif { diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 590e092a1d..d55c522bf3 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -38,7 +38,7 @@ ((1 << CP0C2_M)) /* No config4, no DSP ASE, no large physaddr (PABITS), - no external interrupt controller, no vectored interupts, + no external interrupt controller, no vectored interrupts, no 1kb pages, no SmartMIPS ASE, no trace logic */ #define MIPS_CONFIG3 \ ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ @@ -477,7 +477,7 @@ static const mips_def_t mips_defs[] = .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), .SYNCI_Step = 16, .CCRes = 2, - .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writeable*/ + .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), .SEGBITS = 40, .PABITS = 40, |