diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2013-01-01 18:02:23 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2013-01-31 23:29:36 +0100 |
| commit | ad153f153da08f5e08bc8e433c0070af53e34e0a (patch) | |
| tree | ed063d1f4b6903aeb2ac7961392fb3e138626331 /target-mips | |
| parent | d75c135e6b6255787dfc01ce997862d820ed1d36 (diff) | |
target-mips: generate a reserved instruction exception on CPU without DSP
On CPU without DSP ASE support, a reserved instruction exception (instead of
a DSP ASE sate disabled) should be generated.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index aad5ae4b14..99f3492de2 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1394,14 +1394,22 @@ static inline void check_cp1_registers(DisasContext *ctx, int regs) static inline void check_dsp(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { - generate_exception(ctx, EXCP_DSPDIS); + if (ctx->insn_flags & ASE_DSP) { + generate_exception(ctx, EXCP_DSPDIS); + } else { + generate_exception(ctx, EXCP_RI); + } } } static inline void check_dspr2(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) { - generate_exception(ctx, EXCP_DSPDIS); + if (ctx->insn_flags & ASE_DSP) { + generate_exception(ctx, EXCP_DSPDIS); + } else { + generate_exception(ctx, EXCP_RI); + } } } |