diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-18 03:19:58 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-18 03:19:58 +0000 |
| commit | 8c89395eebc4c88e35949b3310254f0d893379c5 (patch) | |
| tree | 9d2b23a69ac2c0359bf9d9fd33253889b9905793 /target-mips | |
| parent | 7317b8cad72b39bf06d1ce76e20a92c7ef157ba6 (diff) | |
Use a valid PRid.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3685 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index d54e3b6770..f6bda53fec 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -296,7 +296,7 @@ static mips_def_t mips_defs[] = /* A generic CPU providing MIPS64 Release 2 features. FIXME: Eventually this should be replaced by a real CPU model. */ .name = "MIPS64R2-generic", - .CP0_PRid = 0x00000000, + .CP0_PRid = 0x00010000, .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (0x1 << CP0C0_AR), .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |