diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-03 11:06:59 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-03 11:06:59 +0000 |
| commit | 5b2808bfc06279db6a56942f3f6119c23ae07f42 (patch) | |
| tree | d4ff2b1fda588a7e66295131eb34a2f5a78ef4d5 /target-mips | |
| parent | 50cfa95cbd6d0ab896530f7af07a4d5e7539ddc0 (diff) | |
Fix MIPS MT GPR accesses, thanks Stefan Weil.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4307 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/op.c | 16 | ||||
| -rw-r--r-- | target-mips/op_template.c | 4 |
2 files changed, 10 insertions, 10 deletions
diff --git a/target-mips/op.c b/target-mips/op.c index c5187fe9a3..b19c4394b7 100644 --- a/target-mips/op.c +++ b/target-mips/op.c @@ -2300,7 +2300,7 @@ void op_mftgpr(void) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - T0 = env->gpr[PARAM1][other_tc]; + T0 = env->gpr[other_tc][PARAM1]; FORCE_RET(); } @@ -2308,7 +2308,7 @@ void op_mftlo(void) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - T0 = env->LO[PARAM1][other_tc]; + T0 = env->LO[other_tc][PARAM1]; FORCE_RET(); } @@ -2316,7 +2316,7 @@ void op_mfthi(void) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - T0 = env->HI[PARAM1][other_tc]; + T0 = env->HI[other_tc][PARAM1]; FORCE_RET(); } @@ -2324,7 +2324,7 @@ void op_mftacx(void) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - T0 = env->ACX[PARAM1][other_tc]; + T0 = env->ACX[other_tc][PARAM1]; FORCE_RET(); } @@ -2340,7 +2340,7 @@ void op_mttgpr(void) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - T0 = env->gpr[PARAM1][other_tc]; + T0 = env->gpr[other_tc][PARAM1]; FORCE_RET(); } @@ -2348,7 +2348,7 @@ void op_mttlo(void) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - T0 = env->LO[PARAM1][other_tc]; + T0 = env->LO[other_tc][PARAM1]; FORCE_RET(); } @@ -2356,7 +2356,7 @@ void op_mtthi(void) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - T0 = env->HI[PARAM1][other_tc]; + T0 = env->HI[other_tc][PARAM1]; FORCE_RET(); } @@ -2364,7 +2364,7 @@ void op_mttacx(void) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - T0 = env->ACX[PARAM1][other_tc]; + T0 = env->ACX[other_tc][PARAM1]; FORCE_RET(); } diff --git a/target-mips/op_template.c b/target-mips/op_template.c index c683330024..e7e3750fa8 100644 --- a/target-mips/op_template.c +++ b/target-mips/op_template.c @@ -52,13 +52,13 @@ void glue(op_load_gpr_T2_gpr, REG) (void) void glue(op_load_srsgpr_T0_gpr, REG) (void) { - T0 = env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf]; + T0 = env->gpr[(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf][REG]; FORCE_RET(); } void glue(op_store_T0_srsgpr_gpr, REG) (void) { - env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf] = T0; + env->gpr[(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf][REG] = T0; FORCE_RET(); } #endif |