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authorAurelien Jarno <aurelien@aurel32.net>2012-11-14 15:04:42 +0100
committerAurelien Jarno <aurelien@aurel32.net>2012-11-15 14:37:55 +0100
commit68d001928b151a0c50f367c0bdca645b3d5e9ed3 (patch)
treea24065d5220d42e15c16bc0f4846ef56c735d28a /target-mips
parentce34cf72fe508b27a78f83c184142e8d1e6a048a (diff)
mips/malta: fix CBUS UART interrupt pin
According to the MIPS Malta Developement Platform User's Manual, the i8259 interrupt controller is supposed to be connected to the hardware IRQ0, and the CBUS UART to the hardware interrupt 2. In QEMU they are both connected to hardware interrupt 0, the CBUS UART interrupt being wrong. This patch fixes that. It should be noted that the irq array in QEMU includes the software interrupts, hence env->irq[2] is the first hardware interrupt. Cc: Ralf Baechle <ralf@linux-mips.org> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips')
0 files changed, 0 insertions, 0 deletions