diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-12-24 14:33:57 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-12-24 14:33:57 +0000 |
| commit | a1daafd8df0d8acfce48ba220337ef7f895cfd85 (patch) | |
| tree | 767e8612d6af8eeb6b118ef429d2da6150fa099b /target-mips | |
| parent | 33f002714be2ed58ed05ae3870d5ea6915df4b47 (diff) | |
Fix CCRes value for 20Kc.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3849 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 6a4c435768..4958aeb188 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -317,7 +317,7 @@ static mips_def_t mips_defs[] = .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3, .SYNCI_Step = 32, - .CCRes = 2, + .CCRes = 1, .CP0_Status_rw_bitmask = 0x36FBFFFF, /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |