diff options
| author | Andreas Färber <afaerber@suse.de> | 2013-06-21 22:17:17 +0200 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-07-09 21:33:03 +0200 |
| commit | 6429db34c11f8cbb2af446a9c1c80395794e6113 (patch) | |
| tree | 4bad43c956dd6e1be8438a30930b1b88c1d98d9e /target-mips | |
| parent | 4a274212f03adaf8b5971cc39d460335392a97f6 (diff) | |
target-mips: Change gen_intermediate_code_internal() argument to MIPSCPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 160c0c0922..8246c200a1 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15540,9 +15540,10 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) } static inline void -gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb, - int search_pc) +gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, + bool search_pc) { + CPUMIPSState *env = &cpu->env; DisasContext ctx; target_ulong pc_start; uint16_t *gen_opc_end; @@ -15698,12 +15699,12 @@ done_generating: void gen_intermediate_code (CPUMIPSState *env, struct TranslationBlock *tb) { - gen_intermediate_code_internal(env, tb, 0); + gen_intermediate_code_internal(mips_env_get_cpu(env), tb, false); } void gen_intermediate_code_pc (CPUMIPSState *env, struct TranslationBlock *tb) { - gen_intermediate_code_internal(env, tb, 1); + gen_intermediate_code_internal(mips_env_get_cpu(env), tb, true); } static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fpu_fprintf, |