diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-14 03:11:17 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-14 03:11:17 +0000 |
| commit | 3e4587d5d1b8ccb28de9be2fbab724dc1cc89359 (patch) | |
| tree | 1d40a99a148e752e8b4db9d5dc4cf35d2bd7f3de /target-mips/translate_init.c | |
| parent | 1b413d55636c0bc0f615a517e7f29203a787d50c (diff) | |
Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSP
flags.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3637 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 44aff7f37c..d54e3b6770 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -129,6 +129,23 @@ static mips_def_t mips_defs[] = .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, }, { + .name = "4KEm", + .CP0_PRid = 0x00019100, + /* Config1 implemented, MIPS32R2, fixed mapping MMU, + no virtual icache, uncached coherency. */ + .CP0_Config0 = (1 << CP0C0_M) | (0x1 << CP0C0_AR) | + (0x3 << CP0C0_MT) | (0x2 << CP0C0_K0), + .CP0_Config1 = MIPS_CONFIG1 | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + }, + { .name = "24Kc", .CP0_PRid = 0x00019300, .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR), @@ -141,7 +158,7 @@ static mips_def_t mips_defs[] = .CCRes = 2, /* No DSP implemented. */ .CP0_Status_rw_bitmask = 0x1278FF1F, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, }, { .name = "24Kf", @@ -158,7 +175,7 @@ static mips_def_t mips_defs[] = .CP0_Status_rw_bitmask = 0x3678FF1F, .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, }, { .name = "34Kf", |