mips: fix cpu_reset memory leak

Remove cpu_mips_register()
- move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init()
- move the other parts in cpu_mips_init()

Reported-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

1 files changed, 0 insertions, 50 deletions

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index eb35dbad38..088e2b4c29 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -481,8 +481,6 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
         default:
             cpu_abort(env, "MMU type not supported\n");
     }
-    env->CP0_Random = env->tlb->nb_tlb - 1;
-    env->tlb->tlb_in_use = env->tlb->nb_tlb;
 }
 #endif /* CONFIG_USER_ONLY */
 
@@ -530,51 +528,3 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
                              (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
                              (0x1 << CP0MVPC1_PCP1);
 }
-
-static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def)
-{
-    env->CP0_PRid = def->CP0_PRid;
-    env->CP0_Config0 = def->CP0_Config0;
-#ifdef TARGET_WORDS_BIGENDIAN
-    env->CP0_Config0 |= (1 << CP0C0_BE);
-#endif
-    env->CP0_Config1 = def->CP0_Config1;
-    env->CP0_Config2 = def->CP0_Config2;
-    env->CP0_Config3 = def->CP0_Config3;
-    env->CP0_Config6 = def->CP0_Config6;
-    env->CP0_Config7 = def->CP0_Config7;
-    env->SYNCI_Step = def->SYNCI_Step;
-    env->CCRes = def->CCRes;
-    env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask;
-    env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask;
-    env->CP0_SRSCtl = def->CP0_SRSCtl;
-    env->current_tc = 0;
-    env->SEGBITS = def->SEGBITS;
-    env->SEGMask = (target_ulong)((1ULL << def->SEGBITS) - 1);
-#if defined(TARGET_MIPS64)
-    if (def->insn_flags & ISA_MIPS3) {
-        env->hflags |= MIPS_HFLAG_64;
-        env->SEGMask |= 3ULL << 62;
-    }
-#endif
-    env->PABITS = def->PABITS;
-    env->PAMask = (target_ulong)((1ULL << def->PABITS) - 1);
-    env->CP0_SRSConf0_rw_bitmask = def->CP0_SRSConf0_rw_bitmask;
-    env->CP0_SRSConf0 = def->CP0_SRSConf0;
-    env->CP0_SRSConf1_rw_bitmask = def->CP0_SRSConf1_rw_bitmask;
-    env->CP0_SRSConf1 = def->CP0_SRSConf1;
-    env->CP0_SRSConf2_rw_bitmask = def->CP0_SRSConf2_rw_bitmask;
-    env->CP0_SRSConf2 = def->CP0_SRSConf2;
-    env->CP0_SRSConf3_rw_bitmask = def->CP0_SRSConf3_rw_bitmask;
-    env->CP0_SRSConf3 = def->CP0_SRSConf3;
-    env->CP0_SRSConf4_rw_bitmask = def->CP0_SRSConf4_rw_bitmask;
-    env->CP0_SRSConf4 = def->CP0_SRSConf4;
-    env->insn_flags = def->insn_flags;
-
-#ifndef CONFIG_USER_ONLY
-    mmu_init(env, def);
-#endif
-    fpu_init(env, def);
-    mvp_init(env, def);
-    return 0;
-}