diff options
| author | Maciej W. Rozycki <macro@codesourcery.com> | 2014-11-04 15:42:19 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-12-16 12:45:19 +0000 |
| commit | 4386f08767240080334539ac0b07a8bfe30bffe9 (patch) | |
| tree | 6e33377d840b0515a87b5b0b3afc850c89d4b313 /target-mips/translate_init.c | |
| parent | 11f5ea105c06bec72e9bc9a700fa65d60afb5ec3 (diff) | |
target-mips: Enable vectored interrupt support for the 74Kf CPU
Enable vectored interrupt support for the 74Kf CPU, reflecting hardware.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index f0c1072be8..7f73aa2006 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -334,7 +334,7 @@ static const mips_def_t mips_defs[] = (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | - (0 << CP0C3_VInt), + (1 << CP0C3_VInt), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, |