diff options
| author | Leon Alrae <leon.alrae@imgtec.com> | 2014-07-07 11:24:00 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-11-03 11:48:34 +0000 |
| commit | 9456c2fbcd82dd82328ac6e7602a815582b1043e (patch) | |
| tree | 7a2f9f2763b0945ec990ae22f3847476f89c5de5 /target-mips/translate_init.c | |
| parent | 92ceb440d47b9ef3ba860cdc75a7e31563a7dc0c (diff) | |
target-mips: add TLBINV support
For Standard TLB configuration (Config.MT=1):
TLBINV invalidates a set of TLB entries based on ASID. The virtual address is
ignored in the entry match. TLB entries which have their G bit set to 1 are not
modified.
TLBINVF causes all entries to be invalidated.
Single TLB entry can be marked as invalid on TLB entry write by having
EntryHi.EHINV set to 1.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 779afff2d4..bcfc46a715 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -657,6 +657,8 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) env->tlb->helper_tlbwr = r4k_helper_tlbwr; env->tlb->helper_tlbp = r4k_helper_tlbp; env->tlb->helper_tlbr = r4k_helper_tlbr; + env->tlb->helper_tlbinv = r4k_helper_tlbinv; + env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; } static void mmu_init (CPUMIPSState *env, const mips_def_t *def) |