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authorLeon Alrae <leon.alrae@imgtec.com>2014-07-11 16:11:35 +0100
committerLeon Alrae <leon.alrae@imgtec.com>2014-11-03 11:48:34 +0000
commitf31b035a9f10dc9b57f01c426110af845d453ce2 (patch)
treeed772e97f451b594713583a7ce103dbe76638fef /target-mips/translate_init.c
parentba801af429aaa68f6cc03842c8b6be81a6ede65a (diff)
target-mips: correctly handle access to unimplemented CP0 register
Release 6 limits the number of cases where software can cause UNDEFINED or UNPREDICTABLE behaviour. In this case, when accessing reserved / unimplemented CP0 register, writes are ignored and reads return 0. In pre-R6 the behaviour is not specified, but generating RI exception is not what the real HW does. Additionally, remove CP0 Random register as it became reserved in Release 6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target-mips/translate_init.c')
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