diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-12-25 20:46:56 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-12-25 20:46:56 +0000 |
| commit | e9c71dd1c1f5aeb3732261a02dcfae031973f053 (patch) | |
| tree | de9b88fe2a6e0ffbb6b2f1fa63f401e14aa66e6a /target-mips/translate_init.c | |
| parent | 29fe0e3490ef63f564f426fc526d4415f44e7052 (diff) | |
Support for VR5432, and some of its special instructions. Original patch
by Dirk Behme.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3859 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index a2dec0af9f..57666d4db7 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -306,6 +306,22 @@ static mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { + .name = "VR5432", + .CP0_PRid = 0x00005400, + /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ + .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3678FFFF, + /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ + .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 40, + .PABITS = 32, + .insn_flags = CPU_VR54XX, + .mmu_type = MMU_TYPE_R4000, + }, + { .name = "5Kc", .CP0_PRid = 0x00018100, .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |