diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-09-29 19:21:36 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-09-29 19:21:36 +0000 |
| commit | 671880e651e611ec32dbb978e61c0bd4bc3e180e (patch) | |
| tree | a6401fdd2ea52dc7ab54b8721eea7bc820f6c1ad /target-mips/translate_init.c | |
| parent | 544540979cb8ebb4b4ca71bd8df89e5d8e7f8600 (diff) | |
Supervisor mode implementation, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3267 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 6bea0c4d12..b9f3266564 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -141,7 +141,7 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, /* No DSP implemented. */ - .CP0_Status_rw_bitmask = 0x1278FF17, + .CP0_Status_rw_bitmask = 0x1278FF1F, .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, }, { @@ -156,7 +156,7 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, /* No DSP implemented. */ - .CP0_Status_rw_bitmask = 0x3678FF17, + .CP0_Status_rw_bitmask = 0x3678FF1F, .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, @@ -173,7 +173,7 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, /* No DSP implemented. */ - .CP0_Status_rw_bitmask = 0x3678FF17, + .CP0_Status_rw_bitmask = 0x3678FF1F, /* No DSP implemented. */ .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | |