diff options
| author | Leon Alrae <leon.alrae@imgtec.com> | 2016-06-09 10:46:50 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2016-07-12 09:10:14 +0100 |
| commit | 89777fd10fc3dd573c3b4d1b2efdd10af823c001 (patch) | |
| tree | 0b761b2e015b2925b09528a20cab1035a53ce79d /target-mips/translate.c | |
| parent | 19494f811a43c6bc226aa272d86300d9229224fe (diff) | |
target-mips: add exception base to MIPS CPU
Replace hardcoded 0xbfc00000 with exception_base which is initialized with
this default address so there is no functional change here.
However, it is now exposed and consequently it will be possible to modify
it from outside of the CPU.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index cc321e9cce..c302fa3576 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -20169,6 +20169,7 @@ MIPSCPU *cpu_mips_init(const char *cpu_model) cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU)); env = &cpu->env; env->cpu_model = def; + env->exception_base = (int32_t)0xBFC00000; #ifndef CONFIG_USER_ONLY mmu_init(env, def); @@ -20191,6 +20192,12 @@ bool cpu_supports_cps_smp(const char *cpu_model) return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; } +void cpu_set_exception_base(int vp_index, target_ulong address) +{ + MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); + vp->env.exception_base = address; +} + void cpu_state_reset(CPUMIPSState *env) { MIPSCPU *cpu = mips_env_get_cpu(env); @@ -20281,7 +20288,7 @@ void cpu_state_reset(CPUMIPSState *env) } else { env->CP0_ErrorEPC = env->active_tc.PC; } - env->active_tc.PC = (int32_t)0xBFC00000; + env->active_tc.PC = env->exception_base; env->CP0_Random = env->tlb->nb_tlb - 1; env->tlb->tlb_in_use = env->tlb->nb_tlb; env->CP0_Wired = 0; |