diff options
| author | Hervé Poussineau <hpoussin@reactos.org> | 2010-07-31 12:29:03 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-07-31 17:14:52 +0200 |
| commit | 671b0f368bda45e6bcb7a86a6cd49bb90cce3e17 (patch) | |
| tree | ceef4eb85d3fc229bbe0e74cacda1add2ea6344c /target-mips/translate.c | |
| parent | cf7c00d5c6b05c41856f6e957a52a9c34902c48c (diff) | |
Correctly identify multiple cpus in SMP systems
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 6c72dee1ba..20b66a8a51 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12679,8 +12679,7 @@ void cpu_reset (CPUMIPSState *env) env->CP0_Random = env->tlb->nb_tlb - 1; env->tlb->tlb_in_use = env->tlb->nb_tlb; env->CP0_Wired = 0; - /* SMP not implemented */ - env->CP0_EBase = 0x80000000; + env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF); env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); /* vectored interrupts not implemented, timer on int 7, no performance counters. */ |