diff options
| author | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2013-11-29 17:27:42 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2013-12-09 16:41:23 +0100 |
| commit | 4d66261f71f2efa31e1052e4041c5ee505572fe5 (patch) | |
| tree | 495ff45cde07c755d35cde4f28c853fb8b406455 /target-mips/translate.c | |
| parent | 21c046118e740704d0ba81f6281dc95905bc30a8 (diff) | |
target-mips: fix 64-bit FPU config for user-mode emulation
FR bit should be initialized to 1 for MIPS64, under condition that this
bit is writable and that CPU has an FPU unit. It should be initialized to
zero for MIPS32.
This fixes different MIPS32 issues with FPU instructions whose behaviour
defaulted to 64-bit FPU mode.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 67f326b205..e30273438a 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15983,10 +15983,13 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { env->CP0_Status |= (1 << CP0St_MX); } - /* Enable 64-bit FPU if the target cpu supports it. */ - if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { +# if defined(TARGET_MIPS64) + /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ + if ((env->CP0_Config1 & (1 << CP0C1_FP)) && + (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { env->CP0_Status |= (1 << CP0St_FR); } +# endif #else if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot, |