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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-07-12 12:34:41 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-07-12 12:34:41 +0100 |
| commit | 74e1b782b34e280b06a90f61fdbac5a046cbe491 (patch) | |
| tree | 4e707525686a8c338ec5b013189a5f0d586e89a3 /target-mips/translate.c | |
| parent | c1ac514a0444cae0a822dd9a0e60ac77918c102c (diff) | |
| parent | cdc46fab07a122dfcc8a1054510a68d936ae3440 (diff) | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160712' into staging
MIPS patches 2016-07-12
Changes:
* support 10-bit ASIDs
* MIPS64R6-generic renamed to I6400
* initial GIC support
* implement RESET_BASE register in CM GCR
# gpg: Signature made Tue 12 Jul 2016 11:49:50 BST
# gpg: using RSA key 0x52118E3C0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B
* remotes/lalrae/tags/mips-20160712:
target-mips: enable 10-bit ASIDs in I6400 CPU
target-mips: support CP0.Config4.AE bit
target-mips: change ASID type to hold more than 8 bits
target-mips: add ASID mask field and replace magic values
target-mips: replace MIPS64R6-generic with the real I6400 CPU model
hw/mips_cmgcr: implement RESET_BASE register in CM GCR
hw/mips_cpc: make VP correctly start from the reset vector
target-mips: add exception base to MIPS CPU
hw/mips/cps: create GIC block inside CPS
hw/mips: implement Global Interrupt Controller
hw/mips: implement GIC Interval Timer
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index cc321e9cce..bab52cb254 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -20169,6 +20169,7 @@ MIPSCPU *cpu_mips_init(const char *cpu_model) cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU)); env = &cpu->env; env->cpu_model = def; + env->exception_base = (int32_t)0xBFC00000; #ifndef CONFIG_USER_ONLY mmu_init(env, def); @@ -20191,6 +20192,12 @@ bool cpu_supports_cps_smp(const char *cpu_model) return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; } +void cpu_set_exception_base(int vp_index, target_ulong address) +{ + MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); + vp->env.exception_base = address; +} + void cpu_state_reset(CPUMIPSState *env) { MIPSCPU *cpu = mips_env_get_cpu(env); @@ -20281,7 +20288,7 @@ void cpu_state_reset(CPUMIPSState *env) } else { env->CP0_ErrorEPC = env->active_tc.PC; } - env->active_tc.PC = (int32_t)0xBFC00000; + env->active_tc.PC = env->exception_base; env->CP0_Random = env->tlb->nb_tlb - 1; env->tlb->tlb_in_use = env->tlb->nb_tlb; env->CP0_Wired = 0; @@ -20295,6 +20302,8 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { env->CP0_CMGCRBase = 0x1fbf8000 >> 4; } + env->CP0_EntryHi_ASID_mask = (env->CP0_Config4 & (1 << CP0C4_AE)) ? + 0x3ff : 0xff; env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); /* vectored interrupts not implemented, timer on int 7, no performance counters. */ |