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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-06 18:46:01 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-06 18:46:01 +0000 |
| commit | f41c52f17031325652387086006c5847bc703abd (patch) | |
| tree | 7a48f39dd029a1aca329088e9e949c42f16c5221 /target-mips/translate.c | |
| parent | 42a10898a8247821d161e3ac799b758f79fbe3b3 (diff) | |
Save state for all CP0 instructions, they may throw a CPU exception.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2622 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 8da8cc4034..f3b2de446e 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -4880,6 +4880,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) } break; case OPC_CP0: + save_cpu_state(ctx, 1); gen_op_cp0_enabled(); op1 = MASK_CP0(ctx->opcode); switch (op1) { |