diff options
| author | Yongbok Kim <yongbok.kim@imgtec.com> | 2014-11-01 05:28:51 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-11-03 11:48:35 +0000 |
| commit | f7685877f596cfe7e873be5479f975ae985edba9 (patch) | |
| tree | d7ae0b14226adabbbd4ae232b7012bb080e0dc8c /target-mips/translate.c | |
| parent | 3bdeb68866ef2eb212b660381e080f412cc7c817 (diff) | |
target-mips: add MSA MI10 format instructions
add MSA MI10 format instructions
update LSA and DLSA for MSA
add 16, 64 bit load and store
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 49 |
1 files changed, 48 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 73d686e081..2117ce82e0 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -16319,7 +16319,8 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) gen_trap(ctx, op1, rs, rt, -1); break; case OPC_LSA: /* OPC_PMON */ - if (ctx->insn_flags & ISA_MIPS32R6) { + if ((ctx->insn_flags & ISA_MIPS32R6) || + (env->CP0_Config3 & (1 << CP0C3_MSAP))) { decode_opc_special_r6(env, ctx); } else { /* Pmon entry point, also R4010 selsl */ @@ -16417,6 +16418,12 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) break; } break; + case OPC_DLSA: + if ((ctx->insn_flags & ISA_MIPS32R6) || + (env->CP0_Config3 & (1 << CP0C3_MSAP))) { + decode_opc_special_r6(env, ctx); + } + break; #endif default: if (ctx->insn_flags & ISA_MIPS32R6) { @@ -18279,6 +18286,46 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx) case OPC_MSA_VEC: gen_msa_vec(env, ctx); break; + case OPC_LD_B: + case OPC_LD_H: + case OPC_LD_W: + case OPC_LD_D: + case OPC_ST_B: + case OPC_ST_H: + case OPC_ST_W: + case OPC_ST_D: + { + int32_t s10 = sextract32(ctx->opcode, 16, 10); + uint8_t rs = (ctx->opcode >> 11) & 0x1f; + uint8_t wd = (ctx->opcode >> 6) & 0x1f; + uint8_t df = (ctx->opcode >> 0) & 0x3; + + TCGv_i32 tdf = tcg_const_i32(df); + TCGv_i32 twd = tcg_const_i32(wd); + TCGv_i32 trs = tcg_const_i32(rs); + TCGv_i32 ts10 = tcg_const_i32(s10); + + switch (MASK_MSA_MINOR(opcode)) { + case OPC_LD_B: + case OPC_LD_H: + case OPC_LD_W: + case OPC_LD_D: + gen_helper_msa_ld_df(cpu_env, tdf, twd, trs, ts10); + break; + case OPC_ST_B: + case OPC_ST_H: + case OPC_ST_W: + case OPC_ST_D: + gen_helper_msa_st_df(cpu_env, tdf, twd, trs, ts10); + break; + } + + tcg_temp_free_i32(twd); + tcg_temp_free_i32(tdf); + tcg_temp_free_i32(trs); + tcg_temp_free_i32(ts10); + } + break; default: MIPS_INVAL("MSA instruction"); generate_exception(ctx, EXCP_RI); |