diff options
| author | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-01-22 18:35:32 +0100 |
|---|---|---|
| committer | Petar Jovanovic <petar.jovanovic@imgtec.com> | 2014-02-10 16:46:38 +0100 |
| commit | 736d120af4bf5f3e13b2f90c464b3a24847f78f0 (patch) | |
| tree | 01cb88023c2ee383af3dcde2793e756d13b1833e /target-mips/translate.c | |
| parent | b4dd99a3636f5a3044dfd9dba7653ca377a9aeba (diff) | |
target-mips: add user-mode FR switch support for MIPS32r5
Description of UFR feature:
Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by
executing a CFC1 to UFR.
helper_ctc1 has been extended with an additional parameter rt to check
requirements for UFR feature.
Definition of mips32r5-generic has been modified to include support for UFR.
Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 02a90cb532..083f6ab283 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -6818,7 +6818,12 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, break; case 3: /* XXX: For now we support only a single FPU context. */ - gen_helper_0e1i(ctc1, t0, rd); + { + TCGv_i32 fs_tmp = tcg_const_i32(rd); + + gen_helper_0e2i(ctc1, t0, fs_tmp, rt); + tcg_temp_free_i32(fs_tmp); + } break; /* COP2: Not implemented. */ case 4: @@ -7254,7 +7259,12 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) break; case OPC_CTC1: gen_load_gpr(t0, rt); - gen_helper_0e1i(ctc1, t0, fs); + { + TCGv_i32 fs_tmp = tcg_const_i32(fs); + + gen_helper_0e2i(ctc1, t0, fs_tmp, rt); + tcg_temp_free_i32(fs_tmp); + } opn = "ctc1"; break; #if defined(TARGET_MIPS64) |