diff options
| author | Yongbok Kim <yongbok.kim@imgtec.com> | 2015-06-25 00:24:24 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2015-06-26 09:22:25 +0100 |
| commit | 3b4a5489447e7ed17cc504572cf729833853e7ab (patch) | |
| tree | c5f8e95864bd5fecb3fb1ab55d358c5835f91fdd /target-mips/translate.c | |
| parent | 2a24a7badeb6ad3ba72e7984f299623035d564d6 (diff) | |
target-mips: microMIPS32 R6 POOL32{I, C} instructions
Add new microMIPS32 Release 6 POOL32I/POOL32C type instructions
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 27 |
1 files changed, 21 insertions, 6 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 1c9bfdbaa6..1e79c5ab7c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -14666,9 +14666,18 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) check_insn_opc_removed(ctx, ISA_MIPS32R6); mips32_op = OPC_TGEIU; goto do_trapi; - case TNEI: - mips32_op = OPC_TNEI; - goto do_trapi; + case TNEI: /* SYNCI */ + if (ctx->insn_flags & ISA_MIPS32R6) { + /* SYNCI */ + /* Break the TB to be able to sync copied instructions + immediately */ + ctx->bstate = BS_STOP; + } else { + /* TNEI */ + mips32_op = OPC_TNEI; + goto do_trapi; + } + break; case TEQI: check_insn_opc_removed(ctx, ISA_MIPS32R6); mips32_op = OPC_TEQI; @@ -14741,6 +14750,8 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) break; case POOL32C: minor = (ctx->opcode >> 12) & 0xf; + offset = sextract32(ctx->opcode, 0, + (ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12); switch (minor) { case LWL: check_insn_opc_removed(ctx, ISA_MIPS32R6); @@ -14798,23 +14809,27 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) mips32_op = OPC_LL; goto do_ld_lr; do_ld_lr: - gen_ld(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); + gen_ld(ctx, mips32_op, rt, rs, offset); break; do_st_lr: gen_st(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); break; case SC: - gen_st_cond(ctx, OPC_SC, rt, rs, SIMM(ctx->opcode, 0, 12)); + gen_st_cond(ctx, OPC_SC, rt, rs, offset); break; #if defined(TARGET_MIPS64) case SCD: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); - gen_st_cond(ctx, OPC_SCD, rt, rs, SIMM(ctx->opcode, 0, 12)); + gen_st_cond(ctx, OPC_SCD, rt, rs, offset); break; #endif case PREF: /* Treat as no-op */ + if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) { + /* hint codes 24-31 are reserved and signal RI */ + generate_exception(ctx, EXCP_RI); + } break; default: MIPS_INVAL("pool32c"); |