diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2010-03-03 12:22:11 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-03-04 17:42:03 +0100 |
| commit | deb4203dc9ebba6992ac1d583773c143a014e15a (patch) | |
| tree | 28eede5b4a00c3fd32157b02096a43bc47c3e6e6 /target-mips/translate.c | |
| parent | f374e826e340ea1e2de2e9b006b3ac5dbde1324f (diff) | |
target-mips: use newer logical ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 48c65b8cab..0ade3bd48c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1493,9 +1493,8 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, tcg_gen_add_tl(t0, t1, t2); tcg_gen_ext32s_tl(t0, t0); tcg_gen_xor_tl(t1, t1, t2); - tcg_gen_not_tl(t1, t1); tcg_gen_xor_tl(t2, t0, t2); - tcg_gen_and_tl(t1, t1, t2); + tcg_gen_andc_tl(t1, t2, t1); tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); tcg_temp_free(t1); @@ -1571,9 +1570,8 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, gen_load_gpr(t2, rt); tcg_gen_add_tl(t0, t1, t2); tcg_gen_xor_tl(t1, t1, t2); - tcg_gen_not_tl(t1, t1); tcg_gen_xor_tl(t2, t0, t2); - tcg_gen_and_tl(t1, t1, t2); + tcg_gen_andc_tl(t1, t2, t1); tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); tcg_temp_free(t1); @@ -5633,9 +5631,8 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, TCGv_i32 t1 = tcg_temp_new_i32(); tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); - tcg_gen_or_i32(t0, t0, t1); + tcg_gen_nor_i32(t0, t0, t1); tcg_temp_free_i32(t1); - tcg_gen_not_i32(t0, t0); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } @@ -5662,9 +5659,8 @@ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); tcg_gen_or_i32(t0, t0, t1); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); - tcg_gen_or_i32(t0, t0, t1); + tcg_gen_nor_i32(t0, t0, t1); tcg_temp_free_i32(t1); - tcg_gen_not_i32(t0, t0); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } |