diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2013-01-01 18:02:22 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2013-01-31 23:29:27 +0100 |
| commit | f7d2072e25d3592acec4657dae8862facf298e9f (patch) | |
| tree | 7d799c17404cbb21d8c7cc292e0ba825b6afbe49 /target-mips/translate.c | |
| parent | 321f211707822b4c87f0bb89e4f46586fff43163 (diff) | |
target-mips: fix DSP loads with rd = 0
When rd is 0, which still need to do the actually load to possibly
generate a TLB exception.
Reviewed-by: Eric Johnson <ericj@mips.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 206ba83401..a9368294f3 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12657,11 +12657,6 @@ static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, const char *opn = "ldx"; TCGv t0; - if (rd == 0) { - MIPS_DEBUG("NOP"); - return; - } - check_dsp(ctx); t0 = tcg_temp_new(); |