MIPS 64-bit FPU support, plus some collateral bugfixes in the

conditional branch handling.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2779 c046a42c-6fe2-441c-8c8c-71466251a162

1 files changed, 32 insertions, 0 deletions

diff --git a/target-mips/op_mem.c b/target-mips/op_mem.c
index 19373cf002..f0eebc09dd 100644
--- a/target-mips/op_mem.c
+++ b/target-mips/op_mem.c
@@ -220,3 +220,35 @@ void glue(op_sdc1, MEMSUFFIX) (void)
     glue(stq, MEMSUFFIX)(T0, DT0);
     RETURN();
 }
+void glue(op_lwxc1, MEMSUFFIX) (void)
+{
+    WT0 = glue(ldl, MEMSUFFIX)(T0 + T1);
+    RETURN();
+}
+void glue(op_swxc1, MEMSUFFIX) (void)
+{
+    glue(stl, MEMSUFFIX)(T0 + T1, WT0);
+    RETURN();
+}
+void glue(op_ldxc1, MEMSUFFIX) (void)
+{
+    DT0 = glue(ldq, MEMSUFFIX)(T0 + T1);
+    RETURN();
+}
+void glue(op_sdxc1, MEMSUFFIX) (void)
+{
+    glue(stq, MEMSUFFIX)(T0 + T1, DT0);
+    RETURN();
+}
+void glue(op_luxc1, MEMSUFFIX) (void)
+{
+    /* XXX: is defined as unaligned */
+    DT0 = glue(ldq, MEMSUFFIX)(T0 + T1);
+    RETURN();
+}
+void glue(op_suxc1, MEMSUFFIX) (void)
+{
+    /* XXX: is defined as unaligned */
+    glue(stq, MEMSUFFIX)(T0 + T1, DT0);
+    RETURN();
+}