diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-12-06 20:17:30 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-12-06 20:17:30 +0000 |
| commit | 7a387fffce508fedae82e3e81b90d1f20c02c783 (patch) | |
| tree | 1291fac9008d87729c2e129b76aa39e79e4b7436 /target-mips/op_helper.c | |
| parent | 8c0fdd856c63eb11ec5ef955731b1b0cda51f967 (diff) | |
Add MIPS32R2 instructions, and generally straighten out the instruction
decoding. This is also the first percent towards MIPS64 support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2224 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/op_helper.c')
| -rw-r--r-- | target-mips/op_helper.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 11e12c0d84..87a043dc29 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -153,12 +153,12 @@ void cpu_mips_store_compare(CPUState *env, uint32_t value) void do_mtc0_status_debug(uint32_t old, uint32_t val) { - cpu_abort(env, "mtc0 status\n"); + cpu_abort(env, "mtc0 status debug\n"); } -void do_mtc0_status_irqraise_debug(void) +void do_mtc0_status_irqraise_debug (void) { - cpu_abort(env, "mtc0 status\n"); + cpu_abort(env, "mtc0 status irqraise debug\n"); } void do_tlbwi (void) |