diff options
| author | Paul Burton <paul.burton@imgtec.com> | 2016-06-27 16:19:10 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2016-07-12 09:10:19 +0100 |
| commit | 2d72e7b047d800c9f99262466f65a98684ecca14 (patch) | |
| tree | 83f051701fadbd4214f0e23e46881df03c8dddc5 /target-mips/op_helper.c | |
| parent | 6ec98bd7b64ad75870c8e9d87a90fcd1a64b4942 (diff) | |
target-mips: change ASID type to hold more than 8 bits
ASID currently has uint8_t type which is too small since some processors
support more than 8 bits ASID. Therefore change its type to uint16_t.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/op_helper.c')
| -rw-r--r-- | target-mips/op_helper.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 1562f22b5c..31c85f9aee 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2013,7 +2013,7 @@ void r4k_helper_tlbinv(CPUMIPSState *env) { int idx; r4k_tlb_t *tlb; - uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; for (idx = 0; idx < env->tlb->nb_tlb; idx++) { tlb = &env->tlb->mmu.r4k.tlb[idx]; @@ -2039,7 +2039,7 @@ void r4k_helper_tlbwi(CPUMIPSState *env) r4k_tlb_t *tlb; int idx; target_ulong VPN; - uint8_t ASID; + uint16_t ASID; bool G, V0, D0, V1, D1; idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; @@ -2081,7 +2081,7 @@ void r4k_helper_tlbp(CPUMIPSState *env) target_ulong mask; target_ulong tag; target_ulong VPN; - uint8_t ASID; + uint16_t ASID; int i; ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; @@ -2136,7 +2136,7 @@ static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) void r4k_helper_tlbr(CPUMIPSState *env) { r4k_tlb_t *tlb; - uint8_t ASID; + uint16_t ASID; int idx; ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |