diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-13 19:22:13 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-13 19:22:13 +0000 |
| commit | 100ce98812c2624a7e7922055d80ebbd81e8caa9 (patch) | |
| tree | 7f44bac550cbac7dcc5437450242789f447566c1 /target-mips/op.c | |
| parent | f1b0aa5de7f48650aa6260d5dfb8ece1899e286c (diff) | |
Full MIPS64 MMU implementation, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2820 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/op.c')
| -rw-r--r-- | target-mips/op.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target-mips/op.c b/target-mips/op.c index a820aad7b4..ddc3cdea59 100644 --- a/target-mips/op.c +++ b/target-mips/op.c @@ -1317,8 +1317,10 @@ void op_mtc0_entryhi (void) target_ulong old, val; /* 1k pages not implemented */ - /* Ignore MIPS64 TLB for now */ - val = (target_ulong)(int32_t)T0 & ~(target_ulong)0x1F00; + val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF); +#ifdef TARGET_MIPS64 + val = T0 & 0xC00000FFFFFFFFFFULL; +#endif old = env->CP0_EntryHi; env->CP0_EntryHi = val; /* If the ASID changes, flush qemu's TLB. */ |