diff options
| author | Kwok Cheung Yeung <kcy@codesourcery.com> | 2013-05-17 14:51:21 -0700 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2013-05-20 18:16:17 +0200 |
| commit | 1239b472bb0dba8060f1af29d40dafbc1b2860d4 (patch) | |
| tree | 6e2d54f5a06b03a0d274af56cbda5ccb180eeb96 /target-mips/helper.c | |
| parent | ea3164aafccdfdd8a9543787cdfa25fac30a5def (diff) | |
linux-user: Save the correct resume address for MIPS signal handling
The current ISA mode needs to be saved in bit 0 of the resume address.
If the current instruction happens to be in a branch delay slot, then
the address of the preceding jump instruction should be stored instead.
exception_resume_pc already does both of these tasks, so it is
made available and reused.
MIPS_HFLAG_BMASK in hflags is cleared, otherwise QEMU may treat the
first instruction of the signal handler as a delay slot instruction.
Signed-off-by: Kwok Cheung Yeung <kcy@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/helper.c')
| -rw-r--r-- | target-mips/helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-mips/helper.c b/target-mips/helper.c index 3a54acf706..36929ddee7 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -366,8 +366,7 @@ static const char * const excp_names[EXCP_LAST + 1] = { [EXCP_CACHE] = "cache error", }; -#if !defined(CONFIG_USER_ONLY) -static target_ulong exception_resume_pc (CPUMIPSState *env) +target_ulong exception_resume_pc (CPUMIPSState *env) { target_ulong bad_pc; target_ulong isa_mode; @@ -383,6 +382,7 @@ static target_ulong exception_resume_pc (CPUMIPSState *env) return bad_pc; } +#if !defined(CONFIG_USER_ONLY) static void set_hflags_for_handler (CPUMIPSState *env) { /* Exception handlers are entered in 32-bit mode. */ |