diff options
| author | Maciej W. Rozycki <macro@codesourcery.com> | 2014-12-05 18:47:58 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-12-16 12:45:20 +0000 |
| commit | d9224450208e0de62323b64ace91f98bc31d6e2c (patch) | |
| tree | 164e68e82fdd913662ed2c131dc173b2bc92e965 /target-mips/helper.c | |
| parent | 90f12d735d66ac1196d9a2bced039a432eefc03d (diff) | |
target-mips: Tighten ISA level checks
Tighten ISA level checks down to MIPS II that many of our instructions
are missing. Also make sure any 64-bit instruction enables are only
applied to 64-bit processors, that is ones that implement at least the
MIPS III ISA.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/helper.c')
| -rw-r--r-- | target-mips/helper.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/target-mips/helper.c b/target-mips/helper.c index 3a93c206e4..c4b3658098 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -527,7 +527,10 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_DEPC = exception_resume_pc(env); env->hflags &= ~MIPS_HFLAG_BMASK; enter_debug_mode: - env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; + if (env->insn_flags & ISA_MIPS3) { + env->hflags |= MIPS_HFLAG_64; + } + env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0; env->hflags &= ~(MIPS_HFLAG_KSU); /* EJTAG probe trap enable is not implemented... */ if (!(env->CP0_Status & (1 << CP0St_EXL))) @@ -548,7 +551,10 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_ErrorEPC = exception_resume_pc(env); env->hflags &= ~MIPS_HFLAG_BMASK; env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); - env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; + if (env->insn_flags & ISA_MIPS3) { + env->hflags |= MIPS_HFLAG_64; + } + env->hflags |= MIPS_HFLAG_CP0; env->hflags &= ~(MIPS_HFLAG_KSU); if (!(env->CP0_Status & (1 << CP0St_EXL))) env->CP0_Cause &= ~(1U << CP0Ca_BD); @@ -726,7 +732,10 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Cause &= ~(1U << CP0Ca_BD); } env->CP0_Status |= (1 << CP0St_EXL); - env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; + if (env->insn_flags & ISA_MIPS3) { + env->hflags |= MIPS_HFLAG_64; + } + env->hflags |= MIPS_HFLAG_CP0; env->hflags &= ~(MIPS_HFLAG_KSU); } env->hflags &= ~MIPS_HFLAG_BMASK; |