diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-06 10:57:59 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-06 10:57:59 +0000 |
| commit | 958fb4a92cbbb2b9b49e4b4502a836c71435570a (patch) | |
| tree | dc0e1f00ef92b9017ab0ad60e80ba1816766ad56 /target-mips/exec.h | |
| parent | b7ef7bf225416c2d4b9a730feec746c5b60e9655 (diff) | |
Use TCG for MIPS GPR moves.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4356 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/exec.h')
| -rw-r--r-- | target-mips/exec.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-mips/exec.h b/target-mips/exec.h index 5b8206acf7..a8ad0b97c3 100644 --- a/target-mips/exec.h +++ b/target-mips/exec.h @@ -14,8 +14,8 @@ register struct CPUMIPSState *env asm(AREG0); #define T0 (env->t0) #define T1 (env->t1) #else -register target_ulong T0 asm(AREG2); -register target_ulong T1 asm(AREG3); +register target_ulong T0 asm(AREG1); +register target_ulong T1 asm(AREG2); #endif #if defined (USE_HOST_FLOAT_REGS) |