diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-12-30 15:36:58 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-12-30 15:36:58 +0000 |
| commit | b8aa4598e2cc109b0884740a42116acaab01e67d (patch) | |
| tree | 841da3e790c3a04b10dc4a4e96370c1128f8f2dc /target-mips/exec.h | |
| parent | 6341fdcb7841f364a6102ce2b3c375e6c0d7560e (diff) | |
MIPS COP1X (and related) instructions, by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3877 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/exec.h')
| -rw-r--r-- | target-mips/exec.h | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/target-mips/exec.h b/target-mips/exec.h index 7b2c4687f6..35e71e4a75 100644 --- a/target-mips/exec.h +++ b/target-mips/exec.h @@ -237,8 +237,8 @@ static always_inline int cpu_halted(CPUState *env) static always_inline void compute_hflags(CPUState *env) { - env->hflags &= ~(MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | MIPS_HFLAG_F64 | - MIPS_HFLAG_FPU | MIPS_HFLAG_KSU); + env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | + MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU); if (!(env->CP0_Status & (1 << CP0St_EXL)) && !(env->CP0_Status & (1 << CP0St_ERL)) && !(env->hflags & MIPS_HFLAG_DM)) { @@ -257,6 +257,20 @@ static always_inline void compute_hflags(CPUState *env) env->hflags |= MIPS_HFLAG_FPU; if (env->CP0_Status & (1 << CP0St_FR)) env->hflags |= MIPS_HFLAG_F64; + if (env->insn_flags & ISA_MIPS32R2) { + if (env->fpu->fcr0 & FCR0_F64) + env->hflags |= MIPS_HFLAG_COP1X; + } else if (env->insn_flags & ISA_MIPS32) { + if (env->hflags & MIPS_HFLAG_64) + env->hflags |= MIPS_HFLAG_COP1X; + } else if (env->insn_flags & ISA_MIPS4) { + /* All supported MIPS IV CPUs use the XX (CU3) to enable + and disable the MIPS IV extensions to the MIPS III ISA. + Some other MIPS IV CPUs ignore the bit, so the check here + would be too restrictive for them. */ + if (env->CP0_Status & (1 << CP0St_CU3)) + env->hflags |= MIPS_HFLAG_COP1X; + } } #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |