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| author | Anthony Liguori <aliguori@us.ibm.com> | 2013-07-10 10:54:16 -0500 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2013-07-10 10:54:16 -0500 |
| commit | 51455c59ddc370612f6e070d8eb0e594aaa7ef24 (patch) | |
| tree | a3044bd466cb3a548e6abad273663469bf68647a /target-mips/cpu.h | |
| parent | 9f9a03b9818194da39c6759d9b0cbee5d7ace4e1 (diff) | |
| parent | 91b1df8cf9e1ecaa8679c9ea8713d1e25c28e6c4 (diff) | |
Merge remote-tracking branch 'afaerber/tags/qom-cpu-for-anthony' into staging
QOM CPUState refactorings
* Fix for OpenRISCCPU subclasses
* Fix for gdbstub CPU selection
* Move linux-user CPU functions into new header
* CPUState part 10 refactoring: first_cpu, next_cpu, cpu_single_env et al.
* Fix some targets to consistently inline TCG code generation
* Centrally log CPU reset
# gpg: Signature made Wed 10 Jul 2013 07:52:39 AM CDT using RSA key ID 3E7E013F
# gpg: Can't check signature: public key not found
# By Andreas Färber (41) and others
# Via Andreas Färber
* afaerber/tags/qom-cpu-for-anthony: (43 commits)
cpu: Move reset logging to CPUState
target-ppc: Change LOG_MMU_STATE() argument to CPUState
target-i386: Change LOG_PCALL_STATE() argument to CPUState
log: Change log_cpu_state[_mask]() argument to CPUState
target-i386: Change do_smm_enter() argument to X86CPU
target-i386: Change do_interrupt_all() argument to X86CPU
target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU
target-unicore32: Change gen_intermediate_code_internal() signature
target-sparc: Change gen_intermediate_code_internal() argument to SPARCCPU
target-sh4: Change gen_intermediate_code_internal() argument to SuperHCPU
target-s390x: Change gen_intermediate_code_internal() argument to S390CPU
target-ppc: Change gen_intermediate_code_internal() argument to PowerPCCPU
target-mips: Change gen_intermediate_code_internal() argument to MIPSCPU
target-microblaze: Change gen_intermediate_code_internal() argument types
target-m68k: Change gen_intermediate_code_internal() argument to M68kCPU
target-lm32: Change gen_intermediate_code_internal() argument to LM32CPU
target-i386: Change gen_intermediate_code_internal() argument to X86CPU
target-cris: Change gen_intermediate_code_internal() argument to CRISCPU
target-arm: Change gen_intermediate_code_internal() argument to ARMCPU
target-alpha: Change gen_intermediate_code_internal() argument to AlphaCPU
...
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index fa0f0d157f..7ffd2e36bd 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -521,14 +521,6 @@ static inline int cpu_mmu_index (CPUMIPSState *env) return env->hflags & MIPS_HFLAG_KSU; } -static inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp) -{ - if (newsp) - env->active_tc.gpr[29] = newsp; - env->active_tc.gpr[7] = 0; - env->active_tc.gpr[2] = 0; -} - static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) { int32_t pending; @@ -679,11 +671,6 @@ static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); } -static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls) -{ - env->tls_value = newtls; -} - static inline int mips_vpe_active(CPUMIPSState *env) { int active = 1; |