diff options
| author | Leon Alrae <leon.alrae@imgtec.com> | 2014-07-07 11:23:59 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-11-03 11:48:34 +0000 |
| commit | 92ceb440d47b9ef3ba860cdc75a7e31563a7dc0c (patch) | |
| tree | 24224e212514a05c910c299770ffbc101d2f6ba4 /target-mips/cpu.h | |
| parent | 7207c7f9d74816c32783a394d8072d1f978157ac (diff) | |
target-mips: add new Read-Inhibit and Execute-Inhibit exceptions
An Execute-Inhibit exception occurs when the virtual address of an instruction
fetch matches a TLB entry whose XI bit is set. This exception type can only
occur if the XI bit is implemented within the TLB and is enabled, this is
denoted by the PageGrain XIE bit.
An Read-Inhibit exception occurs when the virtual address of a memory load
reference matches a TLB entry whose RI bit is set. This exception type can
only occur if the RI bit is implemented within the TLB and is enabled, this is
denoted by the PageGrain RIE bit.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 38f90f27f4..a9e1bc2eb4 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -247,6 +247,7 @@ struct CPUMIPSState { int32_t CP0_PageGrain; #define CP0PG_RIE 31 #define CP0PG_XIE 30 +#define CP0PG_IEC 27 int32_t CP0_Wired; int32_t CP0_SRSConf0_rw_bitmask; int32_t CP0_SRSConf0; @@ -646,8 +647,10 @@ enum { EXCP_C2E, EXCP_CACHE, /* 32 */ EXCP_DSPDIS, + EXCP_TLBXI, + EXCP_TLBRI, - EXCP_LAST = EXCP_DSPDIS, + EXCP_LAST = EXCP_TLBRI, }; /* Dummy exception for conditional stores. */ #define EXCP_SC 0x100 |