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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-07-12 12:34:41 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-07-12 12:34:41 +0100 |
| commit | 74e1b782b34e280b06a90f61fdbac5a046cbe491 (patch) | |
| tree | 4e707525686a8c338ec5b013189a5f0d586e89a3 /target-mips/cpu.h | |
| parent | c1ac514a0444cae0a822dd9a0e60ac77918c102c (diff) | |
| parent | cdc46fab07a122dfcc8a1054510a68d936ae3440 (diff) | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160712' into staging
MIPS patches 2016-07-12
Changes:
* support 10-bit ASIDs
* MIPS64R6-generic renamed to I6400
* initial GIC support
* implement RESET_BASE register in CM GCR
# gpg: Signature made Tue 12 Jul 2016 11:49:50 BST
# gpg: using RSA key 0x52118E3C0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B
* remotes/lalrae/tags/mips-20160712:
target-mips: enable 10-bit ASIDs in I6400 CPU
target-mips: support CP0.Config4.AE bit
target-mips: change ASID type to hold more than 8 bits
target-mips: add ASID mask field and replace magic values
target-mips: replace MIPS64R6-generic with the real I6400 CPU model
hw/mips_cmgcr: implement RESET_BASE register in CM GCR
hw/mips_cpc: make VP correctly start from the reset vector
target-mips: add exception base to MIPS CPU
hw/mips/cps: create GIC block inside CPS
hw/mips: implement Global Interrupt Controller
hw/mips: implement GIC Interval Timer
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 1037f9b7eb..2c4583931c 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -19,7 +19,7 @@ typedef struct r4k_tlb_t r4k_tlb_t; struct r4k_tlb_t { target_ulong VPN; uint32_t PageMask; - uint8_t ASID; + uint16_t ASID; unsigned int G:1; unsigned int C0:3; unsigned int C1:3; @@ -343,6 +343,7 @@ struct CPUMIPSState { int32_t CP0_Count; target_ulong CP0_EntryHi; #define CP0EnHi_EHINV 10 + target_ulong CP0_EntryHi_ASID_mask; int32_t CP0_Compare; int32_t CP0_Status; #define CP0St_CU3 31 @@ -467,6 +468,7 @@ struct CPUMIPSState { int32_t CP0_Config4_rw_bitmask; #define CP0C4_M 31 #define CP0C4_IE 29 +#define CP0C4_AE 28 #define CP0C4_KScrExist 16 #define CP0C4_MMUExtDef 14 #define CP0C4_FTLBPageSize 8 @@ -503,6 +505,7 @@ struct CPUMIPSState { int CP0_LLAddr_shift; target_ulong CP0_WatchLo[8]; int32_t CP0_WatchHi[8]; +#define CP0WH_ASID 16 target_ulong CP0_XContext; int32_t CP0_Framemask; int32_t CP0_Debug; @@ -616,6 +619,7 @@ struct CPUMIPSState { void *irq[8]; QEMUTimer *timer; /* Internal timer */ MemoryRegion *itc_tag; /* ITC Configuration Tags */ + target_ulong exception_base; /* ExceptionBase input to the core */ }; /** @@ -807,6 +811,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model)) bool cpu_supports_cps_smp(const char *cpu_model); +void cpu_set_exception_base(int vp_index, target_ulong address); /* TODO QOM'ify CPU reset and remove */ void cpu_state_reset(CPUMIPSState *s); |