diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-01-24 18:01:23 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-01-24 18:01:23 +0000 |
| commit | b29a0341d7ed7e7df4bf77a41db8e614f1ddb645 (patch) | |
| tree | 215d496c3ffb1136a1a2c44c4d42fe2da5a6bd0a /target-mips/cpu.h | |
| parent | 4de9b249d37c1b382cc3e5a21fad1b4a11cec2fa (diff) | |
EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2351 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 3c99054d6d..fb5a3fef3d 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -162,7 +162,7 @@ struct CPUMIPSState { #define CP0Ca_EC 2 target_ulong CP0_EPC; int32_t CP0_PRid; - target_ulong CP0_EBase; + int32_t CP0_EBase; int32_t CP0_Config0; #define CP0C0_M 31 #define CP0C0_K23 28 |