diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-02-28 22:37:42 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-02-28 22:37:42 +0000 |
| commit | 36d239587370c6ccfc53d7f6acc624ce5d61fe84 (patch) | |
| tree | 43d11aaf52a198b5544bbb7e878c6cb633dec299 /target-mips/cpu.h | |
| parent | 54d43f70e3b003b5f24ef30ea361e034c2813d9f (diff) | |
MIPS FPU dynamic activation, part 1, by Herve Poussineau.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2463 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 6068813dc6..21651beb0e 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -63,7 +63,6 @@ struct CPUMIPSState { #endif target_ulong HI, LO; uint32_t DCR; /* ? */ -#if defined(MIPS_USES_FPU) /* Floating point registers */ fpr_t fpr[16]; #define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2]) @@ -97,8 +96,7 @@ struct CPUMIPSState { #define FP_DIV0 8 #define FP_INVALID 16 #define FP_UNIMPLEMENTED 32 - -#endif + #if defined(MIPS_USES_R4K_TLB) tlb_t tlb[MIPS_TLB_MAX]; uint32_t tlb_in_use; |