diff options
| author | Kwok Cheung Yeung <kcy@codesourcery.com> | 2013-05-17 14:51:21 -0700 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2013-05-20 18:16:17 +0200 |
| commit | 1239b472bb0dba8060f1af29d40dafbc1b2860d4 (patch) | |
| tree | 6e2d54f5a06b03a0d274af56cbda5ccb180eeb96 /target-mips/cpu.h | |
| parent | ea3164aafccdfdd8a9543787cdfa25fac30a5def (diff) | |
linux-user: Save the correct resume address for MIPS signal handling
The current ISA mode needs to be saved in bit 0 of the resume address.
If the current instruction happens to be in a branch delay slot, then
the address of the preceding jump instruction should be stored instead.
exception_resume_pc already does both of these tasks, so it is
made available and reused.
MIPS_HFLAG_BMASK in hflags is cleared, otherwise QEMU may treat the
first instruction of the signal handler as a delay slot instruction.
Signed-off-by: Kwok Cheung Yeung <kcy@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index cedf03df43..6e761e03b6 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -668,6 +668,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, int rw); #endif +target_ulong exception_resume_pc (CPUMIPSState *env); static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, target_ulong *cs_base, int *flags) |