diff options
| author | Yongbok Kim <yongbok.kim@imgtec.com> | 2015-10-29 15:18:39 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2015-10-30 14:35:52 +0000 |
| commit | b00c72180c36510bf9b124e190bd520e3b7e1358 (patch) | |
| tree | f5a64bd037c0b5577e406da3a7d17f1fc1f5080d /target-mips/cpu.h | |
| parent | ca2f6bbbce32b7e1ba4fdaf54165ab0dee47a3a5 (diff) | |
target-mips: add PC, XNP reg numbers to RDHWR
Add Performance Counter (4) and XNP (5) register numbers to RDHWR.
Add check_hwrena() to simplify access control checkings.
Add RDHWR support to microMIPS R6.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index c68681dec8..fa919c1a13 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -469,6 +469,7 @@ struct CPUMIPSState { #define CP0C5_CV 29 #define CP0C5_EVA 28 #define CP0C5_MSAEn 27 +#define CP0C5_XNP 13 #define CP0C5_UFE 9 #define CP0C5_FRE 8 #define CP0C5_SBRI 6 |