diff options
| author | Edgar E. Iglesias <edgar@axis.com> | 2010-07-24 13:40:05 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2010-07-24 13:40:05 +0200 |
| commit | 36388314febad3d7675ab919287f03733a560ff6 (patch) | |
| tree | 7becf392376dc244c812b5ccd23fd7c227124a0b /target-mips/cpu.h | |
| parent | b2178704e46d061b6162ebd37a19e0db02ccbd77 (diff) | |
mips: Correct MIPS interrupt glue logic for icount
When hw interrupt pending bits in CP0_Cause are set, the CPU should
see the hw interrupt line as active. The CPU may or may not take the
interrupt based on internal state (global irq mask etc) but the glue
logic shouldn't care.
This fixes MIPS external hw interrupts in combination with -icount.
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 81051aa004..157885082a 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -597,9 +597,6 @@ void cpu_mips_store_compare (CPUState *env, uint32_t value); void cpu_mips_start_count(CPUState *env); void cpu_mips_stop_count(CPUState *env); -/* mips_int.c */ -void cpu_mips_update_irq (CPUState *env); - /* helper.c */ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, int mmu_idx, int is_softmmu); |