diff options
| author | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-14 07:07:08 +0000 |
|---|---|---|
| committer | j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-10-14 07:07:08 +0000 |
| commit | 6ebbf390003270afece028facef4d9834df81a8c (patch) | |
| tree | adc8e9a3d586d5b1b550543fceb6ffdaeda03f6a /target-mips/cpu.h | |
| parent | d0f48074dbc21248f3b0a9fb48126cb0d95991b5 (diff) | |
Replace is_user variable with mmu_idx in softmmu core,
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
and using the same definition in code translation code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 137260f329..35bf2fbf6f 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -107,6 +107,8 @@ struct CPUMIPSFPUContext { #define FP_UNIMPLEMENTED 32 }; +#define NB_MMU_MODES 2 + typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; struct CPUMIPSMVPContext { int32_t CP0_MVPControl; @@ -484,6 +486,15 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def); #define cpu_signal_handler cpu_mips_signal_handler #define cpu_list mips_cpu_list +/* MMU modes definitions */ +#define MMU_MODE0_SUFFIX _kernel +#define MMU_MODE1_SUFFIX _user +#define MMU_USER_IDX 1 +static inline int cpu_mmu_index (CPUState *env) +{ + return (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM ? 1 : 0; +} + #include "cpu-all.h" /* Memory access type : |