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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-06-24 21:58:35 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-06-24 21:58:35 +0000 |
| commit | 1a3fd9c3da4e2d9434a14168306b2fa0abadce18 (patch) | |
| tree | 1819501244acc520739c15d158295bf636d46296 /target-mips/cpu.h | |
| parent | e1bf387ec851e56819e4fdd965bc8bdd67167449 (diff) | |
Remove remaining uses of T0 in the MIPS target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4788 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/cpu.h')
| -rw-r--r-- | target-mips/cpu.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index cf7043a576..fdb05ccfd1 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -140,9 +140,6 @@ struct CPUMIPSState { target_ulong gpr[MIPS_SHADOW_SET_MAX][32]; /* Special registers */ target_ulong PC[MIPS_TC_MAX]; -#if TARGET_LONG_BITS > HOST_LONG_BITS - target_ulong t0; -#endif /* temporary hack for FP globals */ #ifndef USE_HOST_FLOAT_REGS fpr_t ft0; |