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| author | Anthony Liguori <aliguori@us.ibm.com> | 2013-02-18 08:37:29 -0600 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2013-02-18 08:37:29 -0600 |
| commit | 3c3adde005ec929d7d581d495d9a0bb223e6e055 (patch) | |
| tree | 05d51a8fa7e87f9ed196b6926c3db84e56c41ca5 /target-mips/cpu-qom.h | |
| parent | f4c0f986c061f34fd5b020c30e2aa8c37e17193b (diff) | |
| parent | 2d64255bd7c0d3933ff5ab2cabff11bcb09117a8 (diff) | |
Merge remote-tracking branch 'afaerber/qom-cpu' into staging
# By Andreas Färber
# Via Andreas Färber
* afaerber/qom-cpu: (47 commits)
target-i386: Split command line parsing out of cpu_x86_register()
target-i386: Move cpu_x86_init()
target-lm32: Drop unused cpu_lm32_close() prototype
target-s390x: Drop unused cpu_s390x_close() prototype
spapr_hcall: Replace open-coded CPU loop with qemu_get_cpu()
ppce500_spin: Replace open-coded CPU loop with qemu_get_cpu()
e500: Replace open-coded loop with qemu_get_cpu()
cpu: Add CPUArchState pointer to CPUState
cputlb: Pass CPUState to cpu_unlink_tb()
cpu: Move current_tb field to CPUState
cpu: Move exit_request field to CPUState
cpu: Move running field to CPUState
cpu: Move host_tid field to CPUState
target-cris: Introduce CRISCPU subclasses
target-m68k: Pass M68kCPU to m68k_set_irq_level()
mcf_intc: Pass M68kCPU to mcf_intc_init()
mcf5206: Pass M68kCPU to mcf5206_init()
target-m68k: Return M68kCPU from cpu_m68k_init()
ppc405_uc: Pass PowerPCCPU to ppc40x_{core,chip,system}_reset()
target-xtensa: Move TCG initialization to XtensaCPU initfn
...
Diffstat (limited to 'target-mips/cpu-qom.h')
| -rw-r--r-- | target-mips/cpu-qom.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h index 2a4b812402..55aa692a85 100644 --- a/target-mips/cpu-qom.h +++ b/target-mips/cpu-qom.h @@ -37,6 +37,7 @@ /** * MIPSCPUClass: + * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * * A MIPS CPU model. @@ -46,6 +47,7 @@ typedef struct MIPSCPUClass { CPUClass parent_class; /*< public >*/ + DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); } MIPSCPUClass; |